REAL

A hierarchical vision processing architecture oriented to 3D integration of smart camera chips

Carmona-Galán, R. and Zarándy, Ákos and Rekeczky, Csaba and Földesy, Péter and Rodríguez-Pérez, A. and Kárász, Zoltán and Roska, Tamás (2013) A hierarchical vision processing architecture oriented to 3D integration of smart camera chips. JOURNAL OF SYSTEMS ARCHITECTURE, 59 (10). pp. 908-919. ISSN 1383-7621

[img] Text
hierarchical_1_s2.0_S138376211300026X_main_u.pdf
Restricted to Repository staff only

Download (3MB) | Request a copy

Abstract

This paper introduces a vision processing architecture that is directly mappable on a 3D chip integration technology. Due to the aggregated nature of the information contained in the visual stimulus, adapted architectures are more efficient than conventional processing schemes. Given the relatively minor importance of the value of an isolated pixel, converting every one of them to digital prior to any processing is inefficient. Instead of this, our system relies on focal-plane image filtering and key point detection for feature extraction. The originally large amount of data representing the image is now reduced to a smaller number of abstracted entities, simplifying the operation of the subsequent digital processor. There are certain limitations to the implementation of such hierarchical scheme. The incorporation of processing elements close to the photo-sensing devices in a planar technology has a negative influence in the fill factor, pixel pitch and image size. It therefore affects the sensitivity and spatial resolution of the image sensor. A fundamental tradeoff needs to be solved. The larger the amount of processing conveyed to the sensor plane, the larger the pixel pitch. On the contrary, using a smaller pixel pitch sends more processing circuitry to the periphery of the sensor and tightens the data bottleneck between the sensor plane and the memory plane. 3D integration technologies with a high density of through-silicon-vias can help overcome these limitations. Vertical integration of the sensor plane and the processing and memory planes with a fully parallel connection eliminates data bottlenecks without compromising fill factor and pixel pitch. A case study is presented: a smart vision chip designed on a 3D integration technology provided by MIT Lincoln Labs, whose base process is 0.15 μm FD-SOI. Simulation results advance performance improvements with respect to the state-of-the-art in smart vision chips. © 2013 Elsevier B.V. All rights reserved.

Item Type: Article
Uncontrolled Keywords: Vision chips; MOPS/mW; Hierarchical vision; Adapted architectures; 3D integrated circuits
Subjects: Q Science / természettudomány > QA Mathematics / matematika > QA75 Electronic computers. Computer science / számítástechnika, számítógéptudomány
SWORD Depositor: MTMT SWORD
Depositing User: MTMT SWORD
Date Deposited: 24 Oct 2016 13:07
Last Modified: 24 Oct 2016 13:07
URI: http://real.mtak.hu/id/eprint/41983

Actions (login required)

Edit Item Edit Item