Reguly, István Zoltán and Mudalige, G.R. and Giles, M. (2017) Loop Tiling in Large-Scale Stencil Codes at Run-time with OPS. IEEE TRANSACTIONS ON PARALLEL AND DISTRIBUTED SYSTEMS, 29 (4). pp. 873-886. ISSN 1045-9219
|
Text
tiling_ext.pdf - Submitted Version Download (665kB) | Preview |
| Item Type: | Article |
|---|---|
| Uncontrolled Keywords: | Tiling; Stencil; OPS; Memory Locality; SCHEDULES; Optimization; LIBRARIES; ELECTRONIC MAIL; DSL; Computer architecture; Algorithm design and analysis |
| Subjects: | Q Science / természettudomány > QA Mathematics / matematika > QA75 Electronic computers. Computer science / számítástechnika, számítógéptudomány |
| SWORD Depositor: | MTMT SWORD |
| Depositing User: | MTMT SWORD |
| Date Deposited: | 14 Sep 2018 06:29 |
| Last Modified: | 14 Sep 2018 06:29 |
| URI: | http://real.mtak.hu/id/eprint/83890 |
Actions (login required)
 |
Edit Item |
